Three-dimensional (3-D) integration is one of important technologies for future integrated circuit design. Semiconductor chips are stacked together and their signals are connected vertically using through silicon vias (TSVs). Comparing with packaging technologies that rely on bond wires, such as system in package (SiP), TSVs provide shorter interconnections between stacked chips, with lower power consumption and higher signal transmission speed. Since TSVs have a much finer pitch than that of bond wires used in SiP, the limitation in available interconnections and the data transmission bottleneck in SiP can be alleviated.
Three-dimensional (3-D) integration technology has been widely used, especially in memory related designs to increase the storage capacity. Three-dimensional random access memory (3-D RAM), which vertically stacks a plurality of memory chips, could apply the TSV interface to access the data of its memory arrays from outside.
With high data bandwidth and large storage capacity targeting at high-performance computing, manufacturing yield becomes a critical issue to make the 3-D RAM practical and mass producible. Comparing with traditional two-dimensional random access memory (2-D RAM) design, the 3-D RAM requires more considerations to sustain a high yield rate. A large number of TSV paths connect the data, address, command, and control signals of the stacked chips from the bottom layer to the top. To guarantee the operations of 3-D RAM, not only each layer of the stacked chips should work properly, but also the TSV paths among layers should be fault-free.